An integrated memory, for example, in the form of a DRAM, generally has a memory cell array comprising word lines and bit lines. In this case, the memory cells are arranged at crossover points of the bit lines and word lines. The memory cells are constructed, in particular, from a storage capacitor and a selection transistor, the selection transistor connecting the respective storage capacitor to one of the bit lines. The control terminals of the respective selection transistors are respectively connected to one of the word lines for the purpose of selecting the memory cells. An activated word line respectively turns on connected selection transistors. After the relevant word line has been selected, data signals of the memory cells along the selected word line are present on the corresponding bit lines. A data signal of a selected memory cell is assessed and amplified in a read/write amplifier of the memory cell array. During a read access, the data signals of selected memory cells are read out for further processing and, during a write access, data signals to be written are written to the selected memory cells.
During a memory access, a word line is first of all activated. As a result, the memory cells arranged along a word line are respectively connected up conductively to a bit line via the relevant selection transistor. In this case, the stored charge is divided up in accordance with the memory cell capacitance and bit line capacitance. In accordance with the ratio of these two capacitances, i.e., a transfer ratio, this leads to deflection of the bit line voltage. The read/write amplifier situated at one end of the bit line can assess this voltage and can amplify the relatively low potential difference until the bit line has reached the full signal level for a stored logic 1 (corresponding, for example, to a positive supply potential) or the signal level for a logic 0 (corresponding, for example, to a reference potential). These full signal levels are provided by a voltage generator circuit, which is connected to the relevant read/write amplifier.
The magnitude of the supply voltage of memories is being constantly reduced, particularly in view of increasing demands for reliability and low energy consumption. In the course of the reduction, modem integrated memories regulate an externally applied supply voltage to a smaller supply voltage within the memory. On the other hand, higher processing speeds of memories and higher data throughput are demanded, particularly on account of increasing memory size. However, it holds true, particularly with regard to the voltage supply for a read/write amplifier of an integrated memory, that a lower supply voltage for reducing the power consumption also leads to a reduction in the switching speed of the relevant read/write amplifier, if the read/write amplifier for the assessment and amplification operation is activated using the lower supply voltage.